Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Power exploration for data dominated video applications
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Compiler-directed scratch pad memory hierarchy design and management
Proceedings of the 39th annual Design Automation Conference
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Reducing energy consumption by dynamic copying of instructions onto onchip memory
Proceedings of the 15th international symposium on System Synthesis
An optimal memory allocation scheme for scratch-pad-based embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Proceedings of the conference on Design, automation and test in Europe
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Cache-Aware Scratchpad Allocation Algorithm
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Data compression for improving SPM behavior
Proceedings of the 41st annual Design Automation Conference
The design and implementation of FIT: a flexible instrumentation toolkit
Proceedings of the 5th ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A post-compiler approach to scratchpad mapping of code
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Proceedings of the international symposium on Code generation and optimization
Dynamic Overlay of Scratchpad Memory for Energy Minimization
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Data partitioning for maximal scratchpad usage
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation
Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs
IEEE Design & Test
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Compiler-guided leakage optimization for banked scratch-pad memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overlay techniques for scratchpad memories in low power embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
Microelectronics Journal
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In VLSI systems-on-chips (SoC), leakage is expected to override 50% of the total power consumption, and the memory sub-system can be responsible for up to 75% of the power. Scratch-pad memories (SPM) are a proven alternative to cache memories in power-aware SoCs. Optimal SPM mapping has already been investigated for dynamic power reduction in the main memory and for leakage reduction in the SPM itself. This paper addresses the problem of global energy optimization (i.e., active+ leakage) in the whole memory sub-system of an SPM-based SoC. We focus on SPMs dedicated to instructions and constant data. We present the technology-level foundation, the mathematical problem formulation, its solution as an integer-linear-programming (ILP) problem, the implemented design flow, and the power reduction results referring to standard benchmarks and ITRS technology data.