Low-power architectural design methodologies
Low-power architectural design methodologies
A specification invariant technique for operation cost minimisation in flow-graphs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formalized methodology for data reuse exploration in hierarchical memory mappings
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low energy memory and register allocation using network flow
DAC '97 Proceedings of the 34th annual Design Automation Conference
DSP address optimization using a minimum cost circulation technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Journal of VLSI Signal Processing Systems - Special issue on system level design
A preprocessing step for global loop transformations for data transfer optimization
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Journal of VLSI Signal Processing Systems
Proceedings of the conference on Design, automation and test in Europe
Systematic data reuse exploration methodology for irregular access patterns
ISSS '00 Proceedings of the 13th international symposium on System synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Array Placement for Storage Size Reduction in Embedded Multimedia Systems
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Architectural Exploration and Optimization for Counter Based Hardware Address Generation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Control Flow Driven Splitting of Loop Nests at the Source Code Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power-aware RAM mapping for FPGA embedded memory blocks
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Reducing off-chip memory access via stream-conscious tiling on multimedia applications
International Journal of Parallel Programming
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Journal of Signal Processing Systems
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
Selective search area reuse algorithm for low external memory access motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Results on leakage power management in scratchpad-based embedded systems
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
A system-level design methodology for application-specific networks-on-chip
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
A combined optimization method for tuning two-level memory hierarchy considering energy consumption
EURASIP Journal on Embedded Systems
Overlay techniques for scratchpad memories in low power embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two iterative metaheuristic approaches to dynamic memory allocation for embedded systems
EvoCOP'11 Proceedings of the 11th European conference on Evolutionary computation in combinatorial optimization
A mathematical model and a metaheuristic approach for a memory allocation problem
Journal of Heuristics
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