REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Unifying data and control transformations for distributed shared-memory machines
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Power exploration for data dominated video applications
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Exact evaluation of memory size for multi-dimensional signal processing systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Allocation of multiport memories for hierarchical data stream
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Parallel Computing - Special issue on applications: parallel processing and multimedia
Memory Reuse Analysis in the Polyhedral Model
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing - Volume I
Fast and extensive system-level memory exploration for ATM applications
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Memory size estimation for multimedia applications
Proceedings of the 6th international workshop on Hardware/software codesign
Exact memory size estimation for array computations without loop unrolling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Shared memory implementations of synchronous dataflow specifications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors
Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing memory requirements of nested loops for embedded systems
Proceedings of the 38th annual Design Automation Conference
Efficient code synthesis from extended dataflow graphs for multimedia applications
Proceedings of the 39th annual Design Automation Conference
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Proceedings of the 12th international symposium on System synthesis
Fractional Rate Dataflow Model for Efficient Code Synthesis
Journal of VLSI Signal Processing Systems
Storage requirement estimation for optimized design of data intensive applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization
Journal of VLSI Signal Processing Systems
A polynomial-time algorithm for memory space reduction
International Journal of Parallel Programming
Optimized memory requirements for wavelet-based scalable multimedia codecs
Journal of Embedded Computing - Low-power Embedded Systems
Fast memory footprint estimation based on maximal dependency vector calculation
Proceedings of the conference on Design, automation and test in Europe
Memory-optimized software synthesis from dataflow program graphs with large size data samples
EURASIP Journal on Applied Signal Processing
A step towards unifying schedule and storage optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Journal of Signal Processing Systems
Buffer sharing in CSP-like programs
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Buffer sharing in rendezvous programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Hi-index | 0.00 |
In this paper we present the second stage of a two-phase strategy for reducing the required background memory sizes for a large class of data-intensive multimedia applications. This strategy is particularly useful in an embedded application context, where memory size and the corresponding power consumption are the main cost factors together with data transfers. Our strategy optimizes the storage order of arrays in memory by trying to improve the reuse of memory locations, as well for elements of the same array as for elements of different arrays. Although size reduction is the main objective, an added benefit is a reduced power consumption due to the decreased capacitive load of the memories. The memory size reduction task is part of an overall memory size and power reduction methodology called ATOMIUM, in which other tasks can increase its effectiveness (e.g. loop transformations), but it can also be used on a stand-alone base. The effectiveness of our approach is demonstrated by experimental results for some real-life multimedia applications, for which a considerable memory size reduction was obtained.