Memory size reduction through storage order optimization for embedded parallel multimedia applications

Energy-Delay Efficient Data Storage and Transfer Architectures and Methodologies: Current Solutions and Remaining Problems

Journal of VLSI Signal Processing Systems - Special issue on system level design

Low power storage cycle budget distribution tool support for hierarchical graphs

ISSS '00 Proceedings of the 13th international symposium on System synthesis

Array Placement for Storage Size Reduction in Embedded Multimedia Systems

ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors

Lattice-based memory allocation

Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems

Optimizing Address Code Generation for Array-Intensive DSP Applications

Proceedings of the international symposium on Code generation and optimization

Lattice-Based Memory Allocation

IEEE Transactions on Computers

An ILP based approach to address code generation for digital signal processors

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose

Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

Mapping multi-dimensional signals into hierarchical memory organizations

Proceedings of the conference on Design, automation and test in Europe

A step towards unifying schedule and storage optimization

ACM Transactions on Programming Languages and Systems (TOPLAS)

Mapping model with inter-array memory sharing for multidimensional signal processing

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Communication between nested loop programs via circular buffers in an embedded multiprocessor system

SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems

Computation of the minimum data storage and applications in memory management for multimedia signal processing

Integrated Computer-Aided Engineering

Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications

Journal of Signal Processing Systems

Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications

Journal of Signal Processing Systems

Trade-offs in loop transformations

ACM Transactions on Design Automation of Electronic Systems (TODAES)

High performance architecture of an application specific processor for the H.264 deblocking filter

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Signal assignment to hierarchical memory organizations for embedded multidimensional signal processing systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs

SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation

Signal Assignment Model for the Memory Management of Multidimensional Signal Processing Applications

Journal of Signal Processing Systems

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA

Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA

Proceedings of the Conference on Design, Automation and Test in Europe

Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes

ACM Transactions on Design Automation of Electronic Systems (TODAES)