The generalized basis reduction algorithm
Mathematics of Operations Research
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Lattice-Based Memory Allocation
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EURASIP Journal on Embedded Systems
Reducing memory requirements of resource-constrained applications
ACM Transactions on Embedded Computing Systems (TECS)
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We investigate the problem of memory reuse, for reducing the necessary memory size, in the context of compilation of dedicated processors. Memory reuse is a well-known concept when allocating registers (i.e., scalar variables). Its (recent) extension to arrays was studied mainly by Lefebvre and Feautrier (for loop parallelization) and by Quilleré and Rajopadhye (for circuit synthesis based on recurrence equations). Both consider affine mappings of indices to data, with modulo expressions in the first and (mainly) projections in the second. We develop a mathematical framework based on (integral) critical lattices that subsumes all previous approaches and gives new insights into the problem. Our technique consists first in building an abstract representation of conflicting indices (equivalent in a multi-dimensional space to the interference graph for register allocation), then in defining an integral lattice, admissible for the set of differences of conflicting indices, used to build a valid modular allocation. We also show the link with critical lattices, successive minima, and basis reduction, and we analyze various strategies for lattice-based memory allocation.