Theory of linear and integer programming
Theory of linear and integer programming
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
A practical algorithm for exact array dependence analysis
Communications of the ACM
Specification and design of embedded systems
Specification and design of embedded systems
A polynomial time algorithm for counting integral points in polyhedra when the dimension is fixed
Mathematics of Operations Research
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Memory estimation for high level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Background memory area estimation for multidimensional signal processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel Computing - Special issue on applications: parallel processing and multimedia
Memory size estimation for multimedia applications
Proceedings of the 6th international workshop on Hardware/software codesign
Automatic storage management for parallel programs
Parallel Computing - Special issues on languages and compilers for parallel computers
Exact memory size estimation for array computations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Optimizing memory usage in the polyhedral model
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reducing memory requirements of nested loops for embedded systems
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 14th international symposium on Systems synthesis
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Storage Size Reduction by In-place Mapping of Arrays
VMCAI '02 Revised Papers from the Third International Workshop on Verification, Model Checking, and Abstract Interpretation
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Lattice-Based Memory Allocation
IEEE Transactions on Computers
Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Computation of storage requirements for multi-dimensional signal processing applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Experiences with enumeration of integer projections of parametric polytopes
CC'05 Proceedings of the 14th international conference on Compiler Construction
Data dependency size estimation for use in memory optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated Computer-Aided Engineering
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The amount of the data storage in signal processing systems, whose behavior is described by loop-organized algorithmic specifications, has an important impact on the overall energy consumption, chip area, as well as system performance. This paper presents a methodology based on lattices [25] which can be used to address several memory management tasks for applications with high-level specifications, where the main data structures are multidimensional arrays. This methodology was used in the past for the exact computation of the minimum data storage in applications with procedural, affine specifications [2]. The paper discusses two applications of that technique in the memory management of data-dominated signal processing systems: (1) the evaluation of the impact of loop transformations on the data storage, and (2) the assessment and efficient implementation of models of mapping multidimensional signals into the physical memory.