Fast and extensive system-level memory exploration for ATM applications
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Exploiting off-chip memory access modes in high-level synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Memory size estimation for multimedia applications
Proceedings of the 6th international workshop on Hardware/software codesign
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Exact memory size estimation for array computations without loop unrolling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Journal of VLSI Signal Processing Systems - Special issue on system level design
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Memory bank customization and assignment in behavioral synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing memory requirements of nested loops for embedded systems
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Automated data dependency size estimation with a partially fixed execution ordering
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Exploring the Number of Register Windows in ASIP Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Optimal Code and Data Layout in Embedded Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Storage requirement estimation for optimized design of data intensive applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A novel memory size model for variable-mapping in system level design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Memory binding for performance optimization of control-flow intensive behavioral descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a multimedia processor based on metrics computation
Advances in Engineering Software - Advanced algorithms and architectures for signal processing
Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Memory size computation for multimedia processing applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Maximizing data reuse for minimizing memory space requirements and execution cycles
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Buffer memory optimization for video codec application modeled in Simulink
Proceedings of the 43rd annual Design Automation Conference
Journal of Embedded Computing - Cache exploitation in embedded systems
Fast memory footprint estimation based on maximal dependency vector calculation
Proceedings of the conference on Design, automation and test in Europe
Incremental hierarchical memory size estimation for steering of loop transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computation of storage requirements for multi-dimensional signal processing applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated Computer-Aided Engineering
Journal of Signal Processing Systems
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Journal of Signal Processing Systems
Integration, the VLSI Journal
Design of a multimedia processor based on metrics computation
Advances in Engineering Software - Advanced algorithms and architectures for signal processing
On minimizing register usage of linearly scheduled algorithms with uniform dependencies
Computer Languages, Systems and Structures
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Experiences with enumeration of integer projections of parametric polytopes
CC'05 Proceedings of the 14th international conference on Compiler Construction
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Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique-founded on data-flow analysis which allows one to address the problem of background memory size evaluation for a given nonprocedural algorithm specification, operating on multidimensional signals with affine indexes. Most of the target applications are characterized by a huge number of signals, so a new polyhedral data-flow model operating on groups of scalar signals is proposed. These groups are obtained by a novel analytical partitioning technique, allowing to select a desired granularity, depending on the application complexity. The method incorporates a way to tradeoff memory size with computational and controller complexity.