High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Memory estimation for high level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Background memory area estimation for multidimensional signal processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of application-specific multiprocessor systems including memory components
Journal of VLSI Signal Processing Systems - Special issue on application specific array processors (ASAP-92)
Exact memory size estimation for array computations without loop unrolling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An optimal memory allocation for application-specific multiprocessor system-on-chip
Proceedings of the 14th international symposium on Systems synthesis
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
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It is predicted that 70% of the chip area will be occupied by memories in future system-on-chips. The minimization of on-chip memory hence becomes increasingly important for cost, performance and energy consumption. This paper proposes a novel memory size model for algorithms which map the variables of a system behavior to memories of a system architecture. To our knowledge, it is the first memory estimation approach that analyzes the variable lifetime for the system behavior, which consists of hierarchically-modelled and concurrently-executed processes and contains variables with different sizes. Experimental results show that significant improvements can be achieved.