Low-swing interconnect interface circuits
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 38th annual Design Automation Conference
Irredundant address bus encoding for low power
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A novel memory size model for variable-mapping in system level design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient exploration of on-chip bus architectures and memory allocation
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automated Bus Generation for Multiprocessor SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
Proceedings of the 43rd annual Design Automation Conference
Software controlled memory layout reorganization for irregular array access patterns
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Using FORAY models to enable MPSoC memory optimizations
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Control flow optimization in loops using interval analysis
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
SPM management using Markov chain based data access prediction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Adaptive scratch pad memory management for dynamic behavior of multimedia applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combined loop transformation and hierarchy allocation for data reuse optimization
Proceedings of the International Conference on Computer-Aided Design
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The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP-based co-synthesis technique, a mixed ILP-based traditional two-step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach.