Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Exploiting the locality of memory references to reduce the address bus energy
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Reducing transitions on memory buses using sector-based encoding technique
Proceedings of the 2002 international symposium on Low power electronics and design
Efficient power reduction techniques for time multiplexed address buses
Proceedings of the 15th international symposium on System Synthesis
Low-power data memory communication for application-specific embedded processors
Proceedings of the 15th international symposium on System Synthesis
A Low Power-Delay Product Page-Based Address Bus Coding Method
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Tiny instruction caches for low power embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power Efficiency through Application-Specific Instruction Memory Transformations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SILENT: serialized low energy transmission coding for on-chip interconnection networks
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
BEAM: bus encoding based on instruction-set-aware memories
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Irredundant address bus encoding techniques based on adaptive codebooks for low power
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Sign Bit Reduction Encoding For Low Power Applications
Journal of Signal Processing Systems
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