Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
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Proceedings of the 37th Annual Design Automation Conference
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Proceedings of the 38th annual Design Automation Conference
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Irredundant address bus encoding for low power
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Narrow bus encoding for low-power DSP systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Low-power data memory communication for application-specific embedded processors
Proceedings of the 15th international symposium on System Synthesis
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Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
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GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
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Proceedings of the conference on Design, automation and test in Europe
Theoretical analysis of bus-invert coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance and power effectiveness in embedded processors customizable partitioned caches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
Low power light-weight embedded systems
Proceedings of the 2006 international symposium on Low power electronics and design
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On-Chip Communication Architectures: System on Chip Interconnect
Sign Bit Reduction Encoding For Low Power Applications
Journal of Signal Processing Systems
An efficient segmental bus-invert coding method for instruction memory data bus switching reduction
EURASIP Journal on Embedded Systems
Journal of Systems Architecture: the EUROMICRO Journal
A power-efficient processor core for reactive embedded applications
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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This paper presents a low-power encoding framework for embedded processor instruction buses. The encoder is capable of adjusting its encoding not only to suit applications but furthermore to suit different aspects of particular program execution. It achieves this by exploiting application-specific knowledge regarding program hot-spots, and thus identifies efficient instruction transformations so as to minimize the bit transitions on the instruction bus lines. Not only is the switching activity on the individual bus lines considered but so is the coupling activity across adjacent bus lines, a foremost contributor to the total power dissipation in the case of nanometer technologies. Low-power codes are utilized in a reprogrammable application specific manner. The restriction to two well-selected classes of simply computable, functional transformations delivers significant storage benefits and ease of reprogrammability, in the process obtaining significant power savings. The microarchitectural support enables reprogrammability of the encoding transformations in order to track code particularities effectively. Such reprogrammability is achieved by utilizing small tables that store relevant application information. The few transformations that result in optimal power reductions for each application hot-spot are selected by utilizing short indices stored into a table, which is accessed only once at the beginning of the transformed bit sequence. Extensive experimental results show significant power reductions ranging up to 80% for switching activity on bus lines and up to 70% when bus coupling effects are also considered.