Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sign Bit Reduction Encoding For Low Power Applications
Journal of Signal Processing Systems
Power modeling of precharged address bus and application to multi-bit DPA attacks to DES algorithm
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Techniques to enhance the resistance of precharged busses to differential power analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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The closed-form formulas derived from the Markov chains depicting the bus-invert coding processes for even and odd bus widths are employed to compute switching activity and weight per bus transfer, to explain the diminishing returns with increasing bus width and to show the nonviability of partitioning a bus into smaller buses of odd number bits, etc. Probing into the codewords generated by the coding process, we obtain the same closed-form formulas as that obtained by the Markov-based approach. Our contributions form a superset over the previously published theoretical results and provide comprehensive background information for exploiting the bus-invert method for low-power applications.