Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Irredundant address bus encoding for low power
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Narrow bus encoding for low-power DSP systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Low power and high speed multiplication design through mixed number representations
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
ALBORZ: Address Level Bus Power Optimization
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Theoretical analysis of bus-invert coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
In this paper, a low power technique, called SBR (Sign Bit Reduction), which reduces the energy consumption in multipliers as well as data buses is proposed. The technique reduces the number of sign bits in the data transfer as well as in the multiplication process. This feature enables us to use the encoding technique for both the transfer of the data and its multiplication at the destination without any need for an intermediate decoding step. Simple circuits are used as the SBR decoder and encoder. The efficacy of the technique is evaluated for both voice and random data. The results of applying the voice data to a 16-bit multiplier implemented with this scheme shows energy consumption up to 11.4% compared to those of a 2's complement implementation, while the number of required clock periods for the multiplication process is reduced up to 14.5%. The results of applying the SBR technique to a 30-tap FIR filter show up to 9.6% reduction in the energy consumption and up to 13.4% reduction in the required clock cycles. Finally, for voice data and random inputs, the use of the technique for a 16-bit data bus leads to an average energy consumption of up to 14.6%.