Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Smart Card Handbook
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Differential Power Analysis in the Presence of Hardware Countermeasures
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
HIDE: an infrastructure for efficiently protecting information leakage on the address bus
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Investigations of power analysis attacks on smartcards
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Theoretical analysis of bus-invert coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A general power model of differential power analysis attacks to static logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power analysis attacks: a novel class of attacks to nanometer cryptographic circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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In this communication, a model of the precharged bus power consumption in digital VLSI circuits is developed. This model is used to analytically evaluate the result of a multi-bit Differential Power Attack (DPA) to the address bus of cryptographic ICs running the DES algorithm. This attack to the address bus is based on the observation of its power consumption, and is well known to be a major threat to the security of the confidential information stored or processed by SmartCards. The results allow to achieve a quantitative model of the DPA attack effectiveness, and is useful as a theoretical basis to understand the trade-offs involved in DPA attacks. This deeper understanding is useful to identify the cases where a SmartCard under attack is weaker with respect to DPA attacks, i.e. when the power consumption reveals the maximum amount of information. Cycle-accurate simulations on DES encryption algorithm running on a MIPS32® architecture are used to validate the model and the underlying assumptions.