A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-effcient physically tagged caches for embedded processors with virtual memory
Proceedings of the 42nd annual Design Automation Conference
Dynamic tag reduction for low-power caches in embedded systems with virtual memory
International Journal of Parallel Programming
Hardware-compiler co-design for adjustable data power savings
Microprocessors & Microsystems
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In this paper, we present a methodology for power minimizationby data cache tag compression. The set of tags being accessed bythe major application loops is analyzed statically during compiletime and an efficient and optimal compression scheme is proposed.Only a very limited number of tag bits are stored in the tag array forcache conflict identification, thus achieving a significant reductionin the number of active bitlines, sense amps, and comparator cells.The underlying hardware support for dynamically compressing thetags consists of a highly cost and power efficient programmableencoder, which lies outside the cache access path, thus not affectingthe processor cycle time. A detailed VLSI implementation hasbeen performed and a number of experimental results on a set ofembedded applications and numerical kernels is reported. Energydissipation decreases of up to 95% can be observed for the tag arrays,while significant energy reductions in the range of 10%-50%are observed when amortized across the overall cache subsystem.