Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Points-to analysis in almost linear time
POPL '96 Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Dynamic IPC/clock rate optimization
Proceedings of the 25th annual international symposium on Computer architecture
Cache-conscious data placement
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Reconfigurable caches and their application to media processing
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
L1 data cache decomposition for energy efficiency
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An efficient profile-analysis framework for data-layout optimizations
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Compiler-directed instruction cache leakage optimization
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A compiler approach for reducing data cache energy
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches
Proceedings of the conference on Design, automation and test in Europe
Interconnect-Centric Array Architectures for Minimum SRAM Access Time
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
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To efficiently accommodate standards changes and algorithmic improvements, functional reconfigurability is increasingly desired for media processing. Such adaptability, however, generally comes at significant power cost. This work suggests that another dimension of adaptation can be beneficial -power adaptation. Through a unique compiler-hardware approach, we (1) demonstrate an extension to the state-of-the-art in data analyzability, yielding better control over scratchpad data management, and (2) combine this knowledge with an SRAM having variable latency and access properties, yielding adjustable power savings. Building upon the compiler techniques presented by [1], we evaluate the severity of the current on-chip storage power problem and detail how SRAM structures can be built to enable data power savings for media applications. We show how the implemented compiler techniques can be applied to other problems in the embedded/media processing domain, and present net data power savings results for a suite of media and telecommunication applications, including MPEG-2, MPEG-4, H.263, and JPEG-2000.