Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Dynamic zero compression for cache energy reduction
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Energy-Efficient Register Access
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Fine-grain CAM-tag cache resizing using miss tags
Proceedings of the 2002 international symposium on Low power electronics and design
Leakage Energy Management in Cache Hierarchies
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Compiler-directed instruction cache leakage optimization
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Managing static leakage energy in microprocessor functional units
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A compiler approach for reducing data cache energy
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Exploiting program hotspots and code sequentiality for instruction cache leakage management
Proceedings of the 2003 international symposium on Low power electronics and design
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
State-Preserving vs. Non-State-Preserving Leakage Control in Caches
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Reducing instruction cache energy consumption using a compiler-based strategy
ACM Transactions on Architecture and Code Optimization (TACO)
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization of logic circuit techniques for high leakage CMOS technologies
Proceedings of the 14th ACM Great Lakes symposium on VLSI
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Implementing branch-predictor decay using quasi-static memory cells
ACM Transactions on Architecture and Code Optimization (TACO)
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Static next sub-bank prediction for drowsy instruction cache
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Energy management in software-controlled multi-level memory hierarchies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
IATAC: a smart predictor to turn-off L2 cache lines
ACM Transactions on Architecture and Code Optimization (TACO)
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Transition aware scheduling: increasing continuous idle-periods in resource units
Proceedings of the 2nd conference on Computing frontiers
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
Optimizing the Thermal Behavior of Subarrayed Data Caches
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Reducing leakage power in instruction cache using WDC for embedded processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Leakage Biased Sleep Switch Domino Logic
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A low energy cache design for multimedia applications exploiting set access locality
Journal of Systems Architecture: the EUROMICRO Journal
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
A case for asymmetric-cell cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microarchitecture-level leakage reduction with data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 20th annual international conference on Supercomputing
Exploiting loop behavior for data cache leakage reduction
Journal of Embedded Computing - Cache exploitation in embedded systems
Reducing branch predictor leakage energy by exploiting loops
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
A new single-ended SRAM cell with write-assist
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage energy reduction in cache memory by data compression
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A distributed processor state management architecture for large-window processors
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Low power and high performance sram design using bank-based selective forward body bias
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Hardware-compiler co-design for adjustable data power savings
Microprocessors & Microsystems
Techniques for leakage energy reduction in deep submicrometer cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Proceedings of the 7th ACM international conference on Computing frontiers
Compiler-guided leakage optimization for banked scratch-pad memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An adaptive technique for reducing leakage and dynamic power in register files and reorder buffers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Hot-and-Cold: using criticality in the design of energy-efficient caches
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Leakage energy reduction in cache memory by software self-invalidation
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic deactivation techniques that include the effects of deactivation energy and startup latencies, as well as long-term leakage current. We present a new circuit-level technique for leakage current reduction, leakage-biased bitlines, that has low deactivation energy and fast wakeup times. We show how this technique can be applied at a fine grain within an active microprocessor, and how microarchitectural scheduling policies can improve its performance. Using leakage-biased bitlines to deactivate SRAM read paths within I-cache memories saves over 24% of leakage energy and 22% of total I-cache energy when using a 70nm process. In the register file, fine-grained read port deactivation saves nearly 50% of leakage energy and 22% of total energy. Independently, turning off idle register file subbanks saves over 67% of leakage energy (57% total register file energy) with no loss in performance.