Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Advanced compiler design and implementation
Advanced compiler design and implementation
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Design Challenges of Technology Scaling
IEEE Micro
Real-Time Task Scheduling for a Variable Voltage Processor
Proceedings of the 12th international symposium on System synthesis
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An energy saving strategy based on adaptive loop parallelization
Proceedings of the 39th annual Design Automation Conference
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
On achieving balanced power consumption in software pipelined loops
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Leakage power modeling and reduction with data retention
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Compiler-directed instruction cache leakage optimization
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Adapting instruction level parallelism for optimizing leakage in VLIW architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
A compiler approach for reducing data cache energy
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Reducing instruction cache energy consumption using a compiler-based strategy
ACM Transactions on Architecture and Code Optimization (TACO)
Optimizing Array-Intensive Applications for On-Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Transition aware scheduling: increasing continuous idle-periods in resource units
Proceedings of the 2nd conference on Computing frontiers
Compiler-guided register reliability improvement against soft errors
Proceedings of the 5th ACM international conference on Embedded software
Variable-Based Multi-module Data Caches for Clustered VLIW Processors
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Journal of VLSI Signal Processing Systems
Loop scheduling with timing and switching-activity minimization for VLIW DSP
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Probabilistic Delay Budgeting for Soft Realtime Applications
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Compiler-directed thermal management for VLIW functional units
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Microarchitecture-level leakage reduction with data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiler-assisted leakage energy optimization for clustered VLIW architectures
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Integration, the VLSI Journal
Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
Journal of Parallel and Distributed Computing
Power consumption and reduction in a real, commercial multimedia core
Proceedings of the 6th ACM conference on Computing frontiers
Compiler-assisted instruction decoder energy optimization for clustered VLIW architectures
HiPC'07 Proceedings of the 14th international conference on High performance computing
Thermal-aware compilation for system-on-chip processing architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Compiler-assisted power optimization for clustered VLIW architectures
Parallel Computing
Probabilistic delay budget assignment for synthesis of soft real-time applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring energy-performance trade-offs for heterogeneous interconnect clustered VLIW processors
HiPC'06 Proceedings of the 13th international conference on High Performance Computing
Compiler analysis and supports for leakage power reduction on microprocessors
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Compile-Time energy optimization for parallel applications in on-chip multiprocessors
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part II
Compiler directed issue queue energy reduction
Transactions on High-Performance Embedded Architectures and Compilers IV
Compiler-assisted energy optimization for clustered VLIW processors
Journal of Parallel and Distributed Computing
| Hi-index | 0.00 |
The mobile computing device market is projected to grow 16.8 million units in 2004, representing an average annual rate of 28% over the five year forecast period [5]. This brings the technologies that optimize system energy to forefront. As circuits continue to scale in future, it would important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels.Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.