Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Performance analysis of tree VLIW architecture for exploiting branch ILP in non-numerical code
ICS '97 Proceedings of the 11th international conference on Supercomputing
Advanced compiler design and implementation
Advanced compiler design and implementation
A framework for dynamic energy efficiency and temperature management
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Compiler optimization on instruction scheduling for low power
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Design Challenges of Technology Scaling
IEEE Micro
Adapting instruction level parallelism for optimizing leakage in VLIW architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Predictive dynamic thermal management for multimedia applications
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Microarchitecture level power and thermal simulation considering temperature dependent leakage model
Proceedings of the 2003 international symposium on Low power electronics and design
Reducing power density through activity migration
Proceedings of the 2003 international symposium on Low power electronics and design
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Efficient Resource Management during Instruction Scheduling for the EPIC Architecture
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Dynamic Functional Unit Assignment for Low Power
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Thermal-Aware Clustered Microarchitectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Distributing the Frontend for Temperature Reduction
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Characterization and modeling of run-time techniques for leakage power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Proactive temperature management in MPSoCs
Proceedings of the 13th international symposium on Low power electronics and design
Thermal-aware post compilation for VLIW architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Static and dynamic temperature-aware scheduling for multiprocessor SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal balancing policy for multiprocessor stream computing platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-aware compilation for system-on-chip processing architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Instruction scheduling for VLIW processors under variation scenario
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Thermal-aware memory mapping in 3D designs
Proceedings of the Conference on Design, Automation and Test in Europe
Reducing functional unit power consumption and its variation using leakage sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiler-assisted power optimization for clustered VLIW architectures
Parallel Computing
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
Thermal-aware datapath merging for coarse-grained reconfigurable processors
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal-aware memory mapping in 3D designs
ACM Transactions on Embedded Computing Systems (TECS)
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As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapath.In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.