Compiler optimization on instruction scheduling for low power

Authors:
Chingren Lee;Jenq Kuen Lee;TingTing Hwang;Shi-Chun Tsai
Affiliations:
Dept. of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Dept. of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Dept. of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Dept. of Information Management, National Chi-Nan University, Pu-Li, Nan-Tou, Taiwan
Venue:
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Year:
2000

Citing 6
Cited 22

Fibonacci heaps and their uses in improved network optimization algorithms

Journal of the ACM (JACM)
Technology decomposition and mapping targeting low power dissipation

DAC '93 Proceedings of the 30th international Design Automation Conference
Precomputation-based sequential logic optimization for low power

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Register allocation and binding for low power

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power analysis and minimization techniques for embedded DSP software

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimization of variable voltage core-based systems

DAC '98 Proceedings of the 35th annual Design Automation Conference

Power-aware modulo scheduling for high-performance VLIW processors

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Efficient instruction-level optimization methodology for low-power embedded systems

Proceedings of the 14th international symposium on Systems synthesis
Energy estimation and optimization of embedded VLIW processors based on instruction clustering

Proceedings of the 39th annual Design Automation Conference
On achieving balanced power consumption in software pipelined loops

CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Compiler optimization on VLIW instruction scheduling for low power

ACM Transactions on Design Automation of Electronic Systems (TODAES)
A trace-based binary compilation framework for energy-aware computing

Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Energy macromodeling of embedded operating systems

ACM Transactions on Embedded Computing Systems (TECS)
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors

IEEE Transactions on Computers
Software-based self-test of processors under power constraints

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Compiler-directed thermal management for VLIW functional units

Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Trace-based leakage energy optimisations at link time

Journal of Systems Architecture: the EUROMICRO Journal
Instruction buffering exploration for low energy embedded processors

Journal of Embedded Computing - Low-power Embedded Systems
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors

International Journal of High Performance Computing and Networking
Highly-cited ideas in system codesign and synthesis

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Automated empirical tuning of scientific codes for performance and power consumption

Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Reliable software for unreliable hardware: embedded code generation aiming at reliability

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Trace-Based data cache leakage reduction at link time

ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Low power microprocessor design for embedded systems

ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
Compiler analysis and supports for leakage power reduction on microprocessors

LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Compiler optimizations with DSP-Specific semantic descriptions

LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Compiler directed issue queue energy reduction

Transactions on High-Performance Embedded Architectures and Compilers IV
Studying the impact of application-level optimizations on the power consumption of multi-core architectures

Proceedings of the 9th conference on Computing Frontiers

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we investigate the compiler transformation techniques to the problem of scheduling VLIW instructions aimed to reduce the power consumption on the instruction bus. It can be categorized into two types: horizontal and vertical scheduling. For the horizontal case, we propose a bipartite-matching scheme. We prove that our greedy algorithm always gives the optimal switching activities of the instruction bus. In the vertical case, we prove that the problem is NP-hard, and propose a heuristic algorithm. Experimental results show average 13% improvements with 4-way issue architecture and average 20% improvement with 8-way issue architecture for power consumptions of instruction bus as compared with conventional list scheduling for an extensive set of benchmarks.