Compiler optimization on instruction scheduling for low power
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Optimized Unrolling of Nested Loops
International Journal of Parallel Programming
Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Analysis of SEU Effects in a Pipelined Processor
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Soft error and energy consumption interactions: a data cache perspective
Proceedings of the 2004 international symposium on Low power electronics and design
SWIFT: Software Implemented Fault Tolerance
Proceedings of the international symposium on Code generation and optimization
Compiler-Directed Instruction Duplication for Soft Error Detection
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Compiler-guided register reliability improvement against soft errors
Proceedings of the 5th ACM international conference on Embedded software
Software-controlled fault tolerance
ACM Transactions on Architecture and Code Optimization (TACO)
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
ICPP '08 Proceedings of the 2008 37th International Conference on Parallel Processing
A compiler optimization to reduce soft errors in register files
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization
ECRTS '09 Proceedings of the 2009 21st Euromicro Conference on Real-Time Systems
Protective redundancy overhead reduction using instruction vulnerability factor
Proceedings of the 7th ACM international conference on Computing frontiers
Software-Implemented Hardware Error Detection: Costs and Gains
DEPEND '10 Proceedings of the 2010 Third International Conference on Dependability
Multicore soft error rate stabilization using adaptive dual modular redundancy
Proceedings of the Conference on Design, Automation and Test in Europe
Design and architectures for dependable embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Reliable computing with ultra-reduced instruction set co-processors
Proceedings of the 49th Annual Design Automation Conference
Instruction scheduling for reliability-aware compilation
Proceedings of the 49th Annual Design Automation Conference
Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic
Proceedings of the International Conference on Computer-Aided Design
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design
Proceedings of the Conference on Design, Automation and Test in Europe
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting program-level masking and error propagation for constrained reliability optimization
Proceedings of the 50th Annual Design Automation Conference
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors
Proceedings of the 50th Annual Design Automation Conference
Reliability challenges for electric vehicles: from devices to architecture and systems software
Proceedings of the 50th Annual Design Automation Conference
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
Power-efficient error-resiliency for H.264/AVC context-adaptive variable length coding
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
An analytical method for reliability aware instruction set extension
The Journal of Supercomputing
Agent-based distributed power management for kilo-core processors
Proceedings of the International Conference on Computer-Aided Design
Formal verification of distributed dynamic thermal management
Proceedings of the International Conference on Computer-Aided Design
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems
Proceedings of the International Conference on Computer-Aided Design
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A compilation technique for reliability-aware software transformations is presented. An instruction-level reliability estimation technique quantifies the effects of hardware-level faults at the instruction-level while considering spatial and temporal vulnerabilities. It bridges the gap between hardware - where faults occur according to our fault model - and software (the abstraction level where we aim to increase reliability). For a given tolerable performance overhead, an optimization algorithm compiles an application software with respect to a tradeoff between performance and reliability. Compared to performance-optimized compilation, our method incurs 60%-80% lower application failures, averaged over various fault injection scenarios and fault rates.