Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation
IEEE Transactions on Software Engineering
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic
DSN '05 Proceedings of the 2005 International Conference on Dependable Systems and Networks
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Exploiting selective placement for low-cost memory protection
ACM Transactions on Architecture and Code Optimization (TACO)
Phaser: phased methodology for modeling the system-level effects of soft errors
IBM Journal of Research and Development
Process variability-aware transient fault modeling and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ESoftCheck: Removal of Non-vital Checks for Fault Tolerance
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Analysis of single-event effects in embedded processors for non-uniform fault tolerant design
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Reliable software for unreliable hardware: embedded code generation aiming at reliability
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Operating system support for redundant multithreading
Proceedings of the tenth ACM international conference on Embedded software
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
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The issue of soft errors is an important emerging concern in the design and implementation of future microprocessors.To date, in all but the most mission-critical applications, implementing parity and Error Correction Codes for caches and other large, regular SRAM structures has been sufficient to stem the growing soft error tide.However, this may not be the case for long, and questions remain as to efficient methods to detect and recover from soft errors - in particular errors in the less structured execution sections. In this work, we examine the impact of soft errors on two different microarchitectures: a simple 5-stage DLX processor and high-performance implementation of an Alpha processor.The results contrast impact of soft errors on combinational and sequential logic, identify the most vulnerable units, and assess the impact of soft errors on the application.