Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Multiple Transient Faults in Logic: An Issue for Next Generation ICs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficient static algorithm for computing the soft error rates of combinational circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Soft error derating computation in sequential circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Scalable techniques and tools for reliability analysis of large circuits
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
An Analysis Framework for Transient-Error Tolerance
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Soft error rate analysis for sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Accurate and scalable reliability analysis of logic circuits
Proceedings of the conference on Design, automation and test in Europe
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reliability-aware design for nanometer-scale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Circuit design and modeling for soft errors
IBM Journal of Research and Development
A systematic approach to modeling and analysis of transient faults in logic circuits
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design as you see FIT: system-level soft error analysis of sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Assessing system vulnerability using formal verification techniques
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
Journal of Electronic Testing: Theory and Applications
Proceedings of the Conference on Design, Automation and Test in Europe
A layout-based approach for multiple event transient analysis
Proceedings of the 50th Annual Design Automation Conference
Quantitative evaluation of soft error injection techniques for robust system design
Proceedings of the 50th Annual Design Automation Conference
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Transient faults in logic circuits are becoming an important reliability concern for future technology nodes. Radiation-induced faults have received significant attention in recent years, while multiple transients originating from a single radiation hit are predicted to occur more often. Furthermore, some effects, like reconvergent fanout-induced glitches, are more pronounced in the case of multiple faults. Therefore, to guide the design process and the choice of circuit optimization techniques, it is important to model multiple faults and their propagation through logic circuits, while evaluating the changes in error rates resulting from multiple simultaneous faults. In this paper, we show how output error probabilities change with increasing number of simultaneous faults and we also analyze the impact of multiple errors in state flip-flops, during the cycles following the cycle when fault(s) occurred. The results obtained using the proposed framework show that output error probability resulting from multiple-event transient or multiple-bit upsets can vary across different outputs and different circuits by several orders of magnitude. The results also show that the impact of different masking factors also varies across circuits and this information can be valuable for customizing protection techniques.