Circuit design and modeling for soft errors

  • Authors:

  • A. KleinOsowski;E. H. Cannon;P. Oldiges;L. Wissel

  • Affiliations:

  • IBM Austin Research Laboratory, Research Division, Austin, Texas;IBM Systems and Technology Group, Essex Junction, Vermont;IBM Semiconductor Research and Development Center, Systems and Technology Group, Hopewell Junction, New York;IBM Systems and Technology Group, Essex Junction, Vermont

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2008

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Abstract

As semiconductor devices decrease in size, soft errors are becoming a major issue that must be addressed at all stages of product definition. Even before prototype silicon chips are available for measuring, modeling must be able to predict soft-error rates with reasonable accuracy. As the technology matures, circuit test sites are produced and experimentally tested to determine representative fail rates of critical SRAM and flip-flop circuits. Circuit models are then fit to these experimental results and further test-site and product circuits are designed and modeled as needed.