IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Soft-error Monte Carlo modeling program, SEMM
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
G4: A Fault-Tolerant CMOS Mainframe
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
POWER5 System microarchitecture
IBM Journal of Research and Development - POWER5 and packaging
SEMM-2: a new generation of single-event-effect modeling tools
IBM Journal of Research and Development
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology
IBM Journal of Research and Development
Alpha-particle-induced upsets in advanced CMOS circuits and technology
IBM Journal of Research and Development
Single-event-upset and alpha-particle emission rate measurement techniques
IBM Journal of Research and Development
Phaser: phased methodology for modeling the system-level effects of soft errors
IBM Journal of Research and Development
System RAS implications of DRAM soft errors
IBM Journal of Research and Development
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
A resilience roadmap: (invited paper)
Proceedings of the Conference on Design, Automation and Test in Europe
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Design sensitivity of single event transients in scaled logic circuits
Proceedings of the 48th Design Automation Conference
Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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As semiconductor devices decrease in size, soft errors are becoming a major issue that must be addressed at all stages of product definition. Even before prototype silicon chips are available for measuring, modeling must be able to predict soft-error rates with reasonable accuracy. As the technology matures, circuit test sites are produced and experimentally tested to determine representative fail rates of critical SRAM and flip-flop circuits. Circuit models are then fit to these experimental results and further test-site and product circuits are designed and modeled as needed.