Phaser: phased methodology for modeling the system-level effects of soft errors

Authors:
J. A. Rivers;P. Bose;P. Kudva;J.-D. Wellman;P. N. Sanda;E. H. Cannon;L. C. Alves
Affiliations:
IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Essex Junction, Vermont;IBM Systems and Technology Group, Poughkeepsie, New York
Venue:
IBM Journal of Research and Development
Year:
2008

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Abstract

This paper presents an overview of Phaser, a toolset and methodology for modeling the effects of soft errors on the architectural and microarchitectural functionality of a system. The Phaser framework is used to understand the system-level effects of soft-error rates of a microprocessor chip as its design evolves through the phases of preconcept, concept, high-level design, and register-transfer-level design implementation. Phaser represents a strategic research vision that is being proposed as a next-generation toolset for predicting chip-level failure rates and studying reliability-performance tradeoffs during the phased design process. This paper primarily presents Phaser/M1, the early stage of the predictive modeling of behavior.