Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
Blue Gene/L torus interconnection network
IBM Journal of Research and Development
Blue Gene/L advanced diagnostics environment
IBM Journal of Research and Development
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Soft-error resilience of the IBM POWER6 processor
IBM Journal of Research and Development
Phaser: phased methodology for modeling the system-level effects of soft errors
IBM Journal of Research and Development
Overview of the Blue Gene/L system architecture
IBM Journal of Research and Development
Blue Gene/L advanced diagnostics environment
IBM Journal of Research and Development
Place and route for massively parallel hardware-accelerated functional verification
Proceedings of the International Conference on Computer-Aided Design
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As 1999 ended, IBM announced its intention to construct a one-petaflop supercomputer. The construction of this system was based on a cellular architecture--the use of relatively small but powerful building blocks used together in sufficient quantities ...