Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
The IBM engineering verification engine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Design hierarchy guided multilevel circuit partitioning
Proceedings of the 2002 international symposium on Physical design
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Software support for the Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Functional verification of the z990 superscalar, multibook microprocessor complex
IBM Journal of Research and Development
Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems
IBM Journal of Research and Development - POWER5 and packaging
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Multidimensional bin packing algorithms
IBM Journal of Research and Development
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
Verification strategy for the Blue Gene/L chip
IBM Journal of Research and Development
Functional verification of the IBM system z10 processor chipset
IBM Journal of Research and Development
Robust partitioning for hardware-accelerated functional verification
Proceedings of the 48th Design Automation Conference
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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Hardware acceleration is a critical component in any modern functional verification methodology. To achieve the best possible utilization, a compiler must intelligently map a logical netlist to the various resources available in the machine architecture. For instance, instructions that serve to route signals between processors must be carefully balanced with those that encode Boolean operations. In addition, chip-to-chip communication should be reduced whilst also ensuring that logic is appropriately partitioned to be executed concurrently. This process is exacerbated by hard constraints on accelerator capacity, as well as rapidly growing industrial designs that approach billions of gates in size. In this paper, we present several compilation strategies that optimize resource allocation to curtail simulation depth, leverage design hierarchy to reduce runtime and memory, and exploit parallel processing to further improve performance. We also review the history of hardware acceleration within IBM, and describe the evolution in architecture that has driven many of these advances in compilation.