Multilevel circuit partitioning

Authors:
Charles J. Alpert;Jen-Hsin Huang;Andrew B. Kahng
Affiliations:
UCLA Computer Science Department, Los Angeles, CA and IBM Austin Research Laboratory, Austin, TX;UCLA Computer Science Department, Los Angeles, CA and Synopsys, Inc., Mountain View, CA;UCLA Computer Science Department, Los Angeles, CA and Cadence Design Systems, Inc., San Jose, CA
Venue:
DAC '97 Proceedings of the 34th annual Design Automation Conference
Year:
1997

Citing 14
Cited 63

Improving the performance of the Kernighan-Lin and simulated annealing graph bisection algorithms

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design

DAC '93 Proceedings of the 30th international Design Automation Conference
Partitioning very large circuits using analytical placement techniques

DAC '94 Proceedings of the 31st annual Design Automation Conference
Graph contraction for mapping data on parallel computers: a quality-cost tradeoff

Scientific Programming
Recent directions in netlist partitioning: a survey

Integration, the VLSI Journal
Linear decomposition algorithm for VLSI design applications

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A probability-based approach to VLSI circuit partitioning

DAC '96 Proceedings of the 33rd annual Design Automation Conference
VLSI circuit partitioning by cluster-removal using iterative improvement techniques

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Partitioning-based standard-cell global placement with an exact objective

Proceedings of the 1997 international symposium on Physical design
An evaluation of bipartitioning techniques

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A linear-time heuristic for improving network partitions

DAC '82 Proceedings of the 19th Design Automation Conference
Multi-way graph and hypergraph partitioning

Multi-way graph and hypergraph partitioning
On implementation choices for iterative improvement partitioning algorithms

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quadratic placement revisited

DAC '97 Proceedings of the 34th annual Design Automation Conference
Hybrid spectral/iterative partitioning

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The ISPD98 circuit benchmark suite

ISPD '98 Proceedings of the 1998 international symposium on Physical design
Partitioning using second-order information and stochastic-gain functions

ISPD '98 Proceedings of the 1998 international symposium on Physical design
Futures for partitioning in physical design (tutorial)

ISPD '98 Proceedings of the 1998 international symposium on Physical design
On multilevel circuit partitioning

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Partitioning by iterative deletion

ISPD '99 Proceedings of the 1999 international symposium on Physical design
Optimal partitioners and end-case placers for standard-cell layout

ISPD '99 Proceedings of the 1999 international symposium on Physical design
Partitioning with terminals: a “new” problem and new benchmarks

ISPD '99 Proceedings of the 1999 international symposium on Physical design
Multilevel k-way hypergraph partitioning

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hypergraph partitioning with fixed vertices

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Relaxation and clustering in a local search framework: application to linear placement

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Can recursive bisection alone produce routable placements?

Proceedings of the 37th Annual Design Automation Conference
Collaborative Web caching based on proxy affinities

Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
A new effective and efficient multi-level partitioning algorithm

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Transformational placement and synthesis

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Further improve circuit partitioning using GBAW logic perturbation techniques

Proceedings of the conference on Design, automation and test in Europe
Improved algorithms for hypergraph bipartitioning

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Multi-way partitioning using bi-partition heuristics

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Watermarking graph partitioning solutions

Proceedings of the 38th annual Design Automation Conference
Improved cut sequences for partitioning based placement

Proceedings of the 38th annual Design Automation Conference
Design and implementation of move-based heuristics for VLSI hypergraph partitioning

Journal of Experimental Algorithmics (JEA)
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Consistent placement of macro-blocks using floorplanning and standard-cell placement

Proceedings of the 2002 international symposium on Physical design
A roadmap and vision for physical design

Proceedings of the 2002 international symposium on Physical design
Effective partition-driven placement with simultaneous level processing and global net views

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On Using Tabu Search for Design Automation of VLSI Systems

Journal of Heuristics
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement

Proceedings of the 2003 international workshop on System-level interconnect prediction
Partition-driven standard cell thermal placement

Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond

Proceedings of the 2003 international symposium on Physical design
Parallel Multilevel Algorithms for Multi-constraint Graph Partitioning (Distinguished Paper)

Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning

ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
Clustering based acyclic multi-way partitioning

Proceedings of the 13th ACM Great Lakes symposium on VLSI
Free space management for cut-based placement

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Further improve circuit partitioning using GBAW logic perturbation techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Recursive bi-partitioning of netlists for large number of partitions

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Placement Using a Localization Probability Model (LPM)

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Implementation and extensibility of an analytic placer

Proceedings of the 2004 international symposium on Physical design
A study of netlist structure and placement efficiency

Proceedings of the 2004 international symposium on Physical design
An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs

IEEE Transactions on Computers
Placement feedback: a concept and method for better min-cut placements

Proceedings of the 41st annual Design Automation Conference
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources

Proceedings of the 41st annual Design Automation Conference
An Enhanced Multilevel Algorithm for Circuit Placement

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Combinatorial techniques for mixed-size placement

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilevel generalized force-directed method for circuit placement

Proceedings of the 2005 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement

Proceedings of the 2005 international symposium on Physical design
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Placement stability metrics

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Architecture and details of a high quality, large-scale analytical placer

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and verification of high-speed VLSI physical design

Journal of Computer Science and Technology
A PROBE-Based Heuristic for Graph Partitioning

IEEE Transactions on Computers
SafeChoice: a novel clustering algorithm for wirelength-driven placement

Proceedings of the 19th international symposium on Physical design
A nondifferentiable optimization approach to ratio-cut partitioning

WEA'03 Proceedings of the 2nd international conference on Experimental and efficient algorithms
Application of fusion-fission to the multi-way graph partitioning problem

PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
Robust partitioning for hardware-accelerated functional verification

Proceedings of the 48th Design Automation Conference
A hierarchical approach for incremental floorplan based on genetic algorithms

ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
Place and route for massively parallel hardware-accelerated functional verification

Proceedings of the International Conference on Computer-Aided Design
Techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systems

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.01

Visualization

Abstract

Recent work has illustrated the promise ofmultilevel approaches for partitioning large circuits. Multilevel partitioningrecursively clusters the instance until its size is smallerthan a given threshold, then unclusters the instance while applyinga partitioning refinement algorithm. Our multilevel partitioner usesa new technique to control the number of levels in the matching-basedclustering phase and also exploits recent innovations in classiciterative partitioning. Our heuristic outperforms numerousexisting bipartitioning heuristics, with improvements rangingfrom 6.9 to 27.9% for 100 runs and 3.0 to 20.6% for just 10 runs(while also using less CPU time).