Multiple-Way Network Partitioning
IEEE Transactions on Computers
Improving the performance of the Kernighan-Lin and simulated annealing graph bisection algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Quadratic Boolean programming for performance-driven system partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
Efficient network flow based min-cut balanced partitioning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-way VLSI circuit partitioning based on dual net representation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Partitioning very large circuits using analytical placement techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Spectral partitioning: the more eigenvectors, the better
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal replication for min-cut partitioning
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A replication cut for two-way partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Network partitioning into tree hierarchies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hybrid spectral/iterative partitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design and implementation of move-based heuristics for VLSI hypergraph partitioning
Journal of Experimental Algorithmics (JEA)
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Replicated partitioning for undirected hypergraphs
Journal of Parallel and Distributed Computing
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In this paper, a Fiduccia-Mattheyses (FM) algorithm incorporating a novel initial partition generating method is proposed. The proposed algorithm applies to both bipartitioning and multi-way partitioning problems with or without replication. The initial partition generating method is based on a gradient decent algorithm. On partitioning without replication, our algorithm achieves an average of 17% improvement over the analytical method, PARABOLI, on bipartitioning, 10% better than Primal-Dual method on 4-way partitioning and 51% better than net-based method. On partitioning allowing replication, our algorithm achieves an average of 23% improvement over the directed Fiduccia-Mattheyses algorithm on Replication Graph (FMRG) method on bipartitioning.