An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits

  • Authors:
  • Jong-Sheng Cherng;Sao-Jie Chen

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '03 Proceedings of the 16th International Conference on VLSI Design
  • Year:
  • 2003

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Abstract

In this paper, a new multi-level bipartitioningalgorithm MLP, which integrates a clustering techniqueand an iterative improvement based partitioning process,is proposed to enhance the stability and the quality ofpartitioning results. The proposed clustering algorithm isused to reduce the partitioning complexity and improvedthe performance of partitioning. To generate a high-qualitypartitioning solution, a module migration basedpartitioning algorithm MMP is also proposed as thebased partitioner for the MLP algorithm. The MMPalgorithm implicitly promotes the move of clusters duringthe module migration processes by paying more attentionto the neighbors of moved modules, relaxing the sizeconstraints temporarily during the migration process, andcontrolling the module migration direction.Experimental results obtained show that the MLPalgorithm generates high-quality partitioning results. TheMLP algorithm outperforms MELO [2] and CDIPLA3 [6] by23% and 10%, respectively and is competitive with hMetis[9] and MLc [1] which have generated better results thanmany recent state-of-the-art partitioning algorithms.