A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
A general framework for vertex orderings, with applications to netlist clustering
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Partitioning very large circuits using analytical placement techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Spectral partitioning: the more eigenvectors, the better
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On implementation choices for iterative improvement partitioning algorithms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A probability-based approach to VLSI circuit partitioning
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New faster Kernighan-Lin-type graph-partitioning algorithms
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Fast and Robust Network Bisection Algorithm
IEEE Transactions on Computers
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Partitioning around roadblocks: tackling constraints with intermediate relaxations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Adaptive methods for netlist partitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hierarchical partitioning for field-programmable systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hybrid spectral/iterative partitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Partitioning using second-order information and stochastic-gain functions
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Circuit partitioning with complex resource constraints in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
On multilevel circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimal partitioners and end-case placers for standard-cell layout
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Partitioning with terminals: a “new” problem and new benchmarks
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hypergraph partitioning with fixed vertices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Effective iterative techniques for fingerprinting design IP
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new effective and efficient multi-level partitioning algorithm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Feasible two-way circuit partitioning with complex resource constraints
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Multi-way partitioning using bi-partition heuristics
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Design and implementation of move-based heuristics for VLSI hypergraph partitioning
Journal of Experimental Algorithmics (JEA)
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effective partition-driven placement with simultaneous level processing and global net views
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On Using Tabu Search for Design Automation of VLSI Systems
Journal of Heuristics
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Proceedings of the 2003 international symposium on Physical design
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
Free space management for cut-based placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Further improve circuit partitioning using GBAW logic perturbation techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs
IEEE Transactions on Computers
Evolutionary Computation - Special issue on magnetic algorithms
Parallel multilevel algorithms for hypergraph partitioning
Journal of Parallel and Distributed Computing
Finding bipartition respecting natural dense clusters
ICC'05 Proceedings of the 9th International Conference on Circuits
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Optimization of parallel FDTD computations based on structural redeployment of macro data flow nodes
PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics
A parallel genetic algorithm based on global program state monitoring
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part I
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Move-based iterative improvement partitioning methods such as the Fiduccia-Mattheyses (FM) algorithm and Krishnamurthy's Look-Ahead (LA) algorithm are widely used in VLSI CAD applications largely due to their time efficiency and ease of implementation. This class of algorithms is of the "local improvement" type. They generate relatively high quality results for small and medium size circuits. However, as VLSI circuits become larger, these algorithms are not so effective on them as direct partitioning tools. We propose new iterative-improvement methods that select cells to move with a view to moving clusters that straddle the two subsets of a partition into one of the subsets. The new algorithms significantly improve partition quality while preserving the advantage of time efficiency. Experimental results on 25 medium to large size ACM/SIGDA benchmark circuits show up to 70% improvement over FM in cutsize, with an average of per-circuit percent improvements of about 25%, and a total cut improvement of about 35%. They also outperform the recent placement-based partitioning tool Paraboli and the spectral partitioner MELO by about 17% and 23%, respectively, with less CPU time. This demonstrates the potential of iterative improvement algorithms in dealing with the increasing complexity of modern VLSI circuitry.