Multiple-Way Network Partitioning with Different Cost Functions
IEEE Transactions on Computers
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
On implementation choices for iterative improvement partitioning algorithms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Partitioning using second-order information and stochastic-gain functions
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Futures for partitioning in physical design (tutorial)
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Hypergraph partitioning with fixed vertices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Cut Size Statistics of Graph Bisection Heuristics
SIAM Journal on Optimization
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An evaluation of bipartitioning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spectral K-way ratio-cut partitioning and clustering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Reporting of standard cell placement results
Proceedings of the 2001 international symposium on Physical design
Design technology productivity in the DSM era (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A roadmap and vision for physical design
Proceedings of the 2002 international symposium on Physical design
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms
IEEE Design & Test
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Placement Using a Localization Probability Model (LPM)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
An analytic placer for mixed-size placement and timing-driven placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Are logic synthesis tools robust?
Proceedings of the 48th Design Automation Conference
Robust partitioning for hardware-accelerated functional verification
Proceedings of the 48th Design Automation Conference
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