Reducing TLB and memory overhead using online superpage promotion
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partitioning using second-order information and stochastic-gain functions
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Futures for partitioning in physical design (tutorial)
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Partitioning with terminals: a “new” problem and new benchmarks
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Iterative improvement based multi-way netlist partitioning for FPGAs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hypergraph partitioning with fixed vertices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Design and implementation of move-based heuristics for VLSI hypergraph partitioning
Journal of Experimental Algorithmics (JEA)
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sequential delay budgeting with interconnect prediction
Proceedings of the 2003 international workshop on System-level interconnect prediction
Wire length prediction in constraint driven placement
Proceedings of the 2003 international workshop on System-level interconnect prediction
Fine granularity clustering for large scale placement problems
Proceedings of the 2003 international symposium on Physical design
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
Hardware-software bipartitioning for dynamically reconfigurable systems
Proceedings of the tenth international symposium on Hardware/software codesign
Wire length prediction based clustering and its application in placement
Proceedings of the 40th annual Design Automation Conference
An Evaluation of Move-Based Multi-Way Partitioning Algorithms
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
International Journal of Reconfigurable Computing
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Logic partitioning is an important issue in VLSI CAD, and has been an area of active research for at least the last 25 years. Numerous approaches have been developed and many different techniques have been combined for a wide range of applications. In this paper, we examine many of the existing techniques for logic bipartitioning and present a methodology for determining the best mix of approaches The result is a novel bipartitioning algorithm that includes both new and preexisting techniques. Our algorithm produces results that are at least 16% better than the state of the art while also being efficient in run time