Linear decomposition algorithm for VLSI design applications
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A probability-based approach to VLSI circuit partitioning
DAC '96 Proceedings of the 33rd annual Design Automation Conference
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Partitioning around roadblocks: tackling constraints with intermediate relaxations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An evaluation of bipartitioning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Design and implementation of move-based heuristics for VLSI hypergraph partitioning
Journal of Experimental Algorithmics (JEA)
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Integration, the VLSI Journal
| Hi-index | 0.00 |
A probability-based partitioning algorithm, PROP, was introduced in [5] that achieved large improvements over traditional “deterministic” iterative-improvement techniques like FM [7] and LA [10]. While PROP's gain function has a greater futuristic component than FM or LA, it incorporates spatially local information—only information on the removal probabilities of adjacent nets of a cell is used in its gain computation. This prevents a higher-level view of non-local structures. Also, giving uniform weights to all nets, results in an inability to differentiate between the futuristic benefit of removing one net from another. In this paper, we present a more sophisticated partitioner DEEP-PROP that incorporates more non-local (second-order) structural information than PROP. The second-order information is incorporated into cell gains as well as variable net weights—the latter helps to focus future cell moves in a cluster around the currently moved cell and thus better utilizes the information that led to its selection. A lower-complexity version, VAR-PROP, that also uses dynamically assigned variable net weights, but based on first-order information, has also been developed. Both versions yield significant improvements over PROP on the ACM/SIGDA benchmark suite. DEEP-PROP yields mincut improvements of as much as 39% for large circuits and an average improvement of 20% over all circuits; it is about 3.8 times slower than PROP, which is very fast. VAR-PROP, which has a much lower computational complexity than DEEP-PROP, yields maximum and average mincut improvements over PROP of 27% and 12%, respectively, while being only about 1.14 times slower.