Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Multiple-Way Network Partitioning with Different Cost Functions
IEEE Transactions on Computers
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
A multilevel algorithm for partitioning graphs
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
On implementation choices for iterative improvement partitioning algorithms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A method for generating random circuits and its application to routability measurement
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Characterization and parameterized random generation of digital circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Partitioning using second-order information and stochastic-gain functions
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Futures for partitioning in physical design (tutorial)
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Multiway partitioning with pairwise movement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Cut Size Statistics of Graph Bisection Heuristics
SIAM Journal on Optimization
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Two novel multiway circuit partitioning algorithms using relaxed locking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An evaluation of bipartitioning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spectral K-way ratio-cut partitioning and clustering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
New challanges in dynamic load balancing
Applied Numerical Mathematics - Adaptive methods for partial differential equations and large-scale computation
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
New challenges in dynamic load balancing
Applied Numerical Mathematics - Adaptive methods for partial differential equations and large-scale computation
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We summarize the techniques of implementing move-based hypergraph partitioning heuristics and evaluating their performance in the context of VLSI design applications. Our first contribution is a detailed software architecture, consisting of seven reusable components, that allows flexible, efficient and accurate assessment of the practical implications of new move-based algorithms and partitioning formulations. Our second contribution is an assessment of the modern context for hypergraph partitioning research for VLSI design applications. In particular, we discuss the current level of sophistication in implementation know-how and experimental evaluation, and we note how requirements for real-world partitioners - if used as motivation for research - should affect the evaluation of prospective contributions. Two "implicit decisions" in the implementation of the Fiduccia-Mattheyses heuristic are used to illustrate the difficulty of achieving meaningful experimental evaluation of new algorithmic ideas.