Benchmarks for layout synthesis—evolution and current status
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A new performance driven placement method with the Elmore delay model for row based VLSIs
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
Partitioning around roadblocks: tackling constraints with intermediate relaxations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimal partitioners and end-case placers for standard-cell layout
ISPD '99 Proceedings of the 1999 international symposium on Physical design
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Multi-way partitioning using bi-partition heuristics
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Design and implementation of move-based heuristics for VLSI hypergraph partitioning
Journal of Experimental Algorithmics (JEA)
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A combined force and cut algorithm for hierarchical VLSI layout
DAC '82 Proceedings of the 19th Design Automation Conference
Min-cut placement with global objective functions for large scale sea-of-gates arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wirelength estimation based on rent exponents of partitioning and placement
Proceedings of the 2001 international workshop on System-level interconnect prediction
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
Interconnect implications of growth-based structural models for VLSI circuits
Proceedings of the 2001 international workshop on System-level interconnect prediction
Global objectives for standard cell placement
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Reporting of standard cell placement results
Proceedings of the 2001 international symposium on Physical design
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
Improved cut sequences for partitioning based placement
Proceedings of the 38th annual Design Automation Conference
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
A roadmap and vision for physical design
Proceedings of the 2002 international symposium on Physical design
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
FAR: fixed-points addition & relaxation based placement
Proceedings of the 2002 international symposium on Physical design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Congestion reduction during placement based on integer programming
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms
IEEE Design & Test
Wire length prediction in constraint driven placement
Proceedings of the 2003 international workshop on System-level interconnect prediction
Fine granularity clustering for large scale placement problems
Proceedings of the 2003 international symposium on Physical design
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
FORCE: a fast and easy-to-implement variable-ordering heuristic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Design topology aware physical metrics for placement analysis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Congestion reduction in traditional and new routing architectures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Congestion minimization during placement without estimation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Free space management for cut-based placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Wire length prediction based clustering and its application in placement
Proceedings of the 40th annual Design Automation Conference
Congestion reduction during placement with provably good approximation bound
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Boosting: Min-Cut Placement with Improved Signal Delay
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Innovate or perish: FPGA physical design
Proceedings of the 2004 international symposium on Physical design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
A predictive distributed congestion metric and its application to technology mapping
Proceedings of the 2004 international symposium on Physical design
Constructive benchmarking for placement
Proceedings of the 14th ACM Great Lakes symposium on VLSI
On legalization of row-based placements
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Timing, energy, and thermal performance of three-dimensional integrated circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
On designing via-configurable cell blocks for regular fabrics
Proceedings of the 41st annual Design Automation Conference
Large-scale placement by grid-warping
Proceedings of the 41st annual Design Automation Conference
Placement feedback: a concept and method for better min-cut placements
Proceedings of the 41st annual Design Automation Conference
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources
Proceedings of the 41st annual Design Automation Conference
Placement Method Targeting Predictability Robustness and Performance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Evaluation of Placement Techniques for DNA Probe Array Layout
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Trade-off Oriented Placement Tool
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Active mode leakage reduction using fine-grained forward body biasing strategy
Proceedings of the 2004 international symposium on Low power electronics and design
Robust fixed-outline floorplanning through evolutionary search
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Calibration of rent's rule models for three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Improved Multi-Level Framework for Force-Directed Placement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Toward Quality EDA Tools and Tool Flows Through High-Performance Computing
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Congestion prediction in early stages
Proceedings of the 2005 international workshop on System level interconnect prediction
Proceedings of the 2005 international symposium on Physical design
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
Evaluation of placer suboptimality via zero-change netlist transformations
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Timing-driven placement by grid-warping
Proceedings of the 42nd annual Design Automation Conference
Faster and better global placement by a new transportation algorithm
Proceedings of the 42nd annual Design Automation Conference
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Leakage control through fine-grained placement and sizing of sleep transistors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A new incremental placement algorithm and its application to congestion-aware divisor extraction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An analytic placer for mixed-size placement and timing-driven placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multilevel expansion-based VLSI placement with blockages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing-driven placement based on monotone cell ordering constraints
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Simultaneous block and I/O buffer floorplanning for flip-chip design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Congestion prediction in floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal placement by branch-and-price
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Robust mixed-size placement under tight white-space constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A hybrid linear equation solver and its application in quadratic placement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
On whitespace and stability in physical synthesis
Integration, the VLSI Journal
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A morphing approach to address placement stability
Proceedings of the 2007 international symposium on Physical design
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Trunk decomposition based global routing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Active mode leakage reduction using fine-grained forward body biasing strategy
Integration, the VLSI Journal
Postplacement rewiring by exhaustive search for functional symmetries
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
DPlace2.0: a stable and efficient analytical placement based on diffusion
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
SafeResynth: A new technique for physical synthesis
Integration, the VLSI Journal
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Congestion prediction in early stages of physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solving modern mixed-size placement instances
Integration, the VLSI Journal
Practical, fast Monte Carlo statistical static timing analysis: why and how
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Hardware accelerated FPGA placement
Microelectronics Journal
A study of routability estimation and clustering in placement
Proceedings of the 2009 International Conference on Computer-Aided Design
Parallel multi-level analytical global placement on graphics processing units
Proceedings of the 2009 International Conference on Computer-Aided Design
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
Register pressure aware scheduling for high level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
StarPlace: A new analytic method for FPGA placement
Integration, the VLSI Journal
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
A hierarchical approach for incremental floorplan based on genetic algorithms
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Artificial bee colony for the standard cell placement problem
International Journal of Metaheuristics
The impact of shallow trench isolation effects on circuit performance
Proceedings of the International Conference on Computer-Aided Design
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This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the state-of-the-art after two decades of research in recursive bisection placement and implement a new placer, called Capo, to empirically study the achievable limits of the approach. From among recently proposed improvements to recursive bisection, Capo incorporates a leading-edge multilevel min-cut partitioner [7], techniques for partitioning with small tolerance [8], optimal min-cut partitioners and end-case min-wirelength placers [5], previously unpublished partitioning tolerance computations, and block splitting heuristics. On the other hand, our “good enough” implementation does not use “overlapping” [17], multi-way partitioners [17, 20], analytical placement, or congestion estimation [24, 35]. In order to run on recent industrial placement instances, Capo must take into account fixed macros, power stripes and rows with different allowed cell orientations. Capo reads industry-standard LEF/DEF, as well as formats of the GSRC bookshelf for VLSI CAD algorithms [6], to enable comparisons on available placement instances in the fixed-die regime.Capo clearly demonstrates that despite a potential mismatch of objectives, improved mincut bisection can still lead to improved placement wirelength and congestion. Our experiments on recent industrial benchmarks fail to give a clear answer to the question in the title of this paper. However, they validate a series of improvements to recursive bisection and point out a need for transparent congestion management techniques that do not worsen the wirelength of already routable placements. Our experimental flow, which validates fixed-die placement results by violation-free detailed auto-routability, provides a new norm for comparison of VLSI placement implementations.