A fast physical constraint generator for timing driven layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing-driven placement based on partitioning with dynamic cut-net control
Proceedings of the 37th Annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
A performance-driven standard-cell placer based on a modified force-directed algorithm
Proceedings of the 2001 international symposium on Physical design
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
Physical hierarchy generation with routing congestion control
Proceedings of the 2002 international symposium on Physical design
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Potential slack: an effective metric of combinational circuit performance
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential delay budgeting with interconnect prediction
Proceedings of the 2003 international workshop on System-level interconnect prediction
Wire length prediction in constraint driven placement
Proceedings of the 2003 international workshop on System-level interconnect prediction
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Quadratic placement using an improved timing model
Proceedings of the 41st annual Design Automation Conference
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2005 international symposium on Physical design
Dragon2005: large-scale mixed-size placement tool
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An analytic placer for mixed-size placement and timing-driven placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing-driven placement based on monotone cell ordering constraints
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
A network-flow approach to timing-driven incremental placement for ASICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Post sign-off leakage power optimization
Proceedings of the 48th Design Automation Conference
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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Design hierarchy plays an important role in timing-driven placement for large circuits. In this paper, we present a new methodology for delay budgeting based timing-driven placement. A novel slack assignment approach is described as well as its application on delay budgeting with design hierarchy information. The proposed timing-driven placement flow is implemented into a placement tool named Dragon (timing-driven mode), and evaluated using an industrial place and route flow. Compared to Cadence QPlace, timing-driven Dragon generates placement results with shorter clock cycle and better routability.