Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reporting of standard cell placement results
Proceedings of the 2001 international symposium on Physical design
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Standard-Cell Placement Tool for Designs with High Row Utilization
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A tale of two nets: studies of wirelength progression in physical design
Proceedings of the 2006 international workshop on System-level interconnect prediction
A robust detailed placement for mixed-size IC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Effective linear programming based placement methods
Proceedings of the 2006 international symposium on Physical design
Dragon2006: blockage-aware congestion-controlling mixed-size placer
Proceedings of the 2006 international symposium on Physical design
NTUplace2: a hybrid placer using partitioning and analytical techniques
Proceedings of the 2006 international symposium on Physical design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Mixed-size placement via line search
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
Fast and robust quadratic placement combined with an exact linear net model
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
Solving modern mixed-size placement instances
Integration, the VLSI Journal
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Towards scalable placement for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Speeding up FPGA placement via partitioning and multithreading
International Journal of Reconfigurable Computing
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Cell density-driven detailed placement with displacement constraint
Proceedings of the 2014 on International symposium on physical design
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In this paper, we develop a mixed-size placement tool, Dragon2005, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partitioning and simulated annealing is used to place very large SoC-style designs containing thousands of macro blocks of various sizes and millions of standard cells. Macro aware partitioning and techniques to properly handle different bin sizes are required, because of the existence of large macro blocks. Our tool is also a congestion and timing aware placement tool.