Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
On legalization of row-based placements
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
Unified quadratic programming approach for mixed mode placement
Proceedings of the 2005 international symposium on Physical design
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
Proceedings of the 2005 international symposium on Physical design
Dragon2005: large-scale mixed-size placement tool
Proceedings of the 2005 international symposium on Physical design
An analytic placer for mixed-size placement and timing-driven placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A robust detailed placement for mixed-size IC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The ISPD global routing benchmark suite
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Cell transformations and physical design techniques for 3D monolithic integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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In this paper, we present a hybrid placer, called NTUplace2, which integrates both the partitioning and the analytical (quadratic programming) placement techniques for large-scale mixed-size designs. Unlike most existing placers that minimize wirelength alone, we also control the cell density to optimize routability while minimizing the total wirelength. NTUplace2 consists of three major stages: multilevel global placement, legalization, and detailed placement. To handle mixed-size designs, in particular, we present a linear programming based legalization algorithm to remove overlaps between macros during global placement. Various other techniques are integrated to improve the solution quality at every stage.