CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Authors:
Shashikanth Bobba;Ashutosh Chakraborty;Olivier Thomas;Perrine Batude;Thomas Ernst;Olivier Faynot;David Z. Pan;Giovanni De Micheli
Affiliations:
Integrated Systems Laboratory (LSI), EPFL, Switzerland;University of Texas Austin;CEA-LETI/MINATEC, France;CEA-LETI/MINATEC, France;CEA-LETI/MINATEC, France;CEA-LETI/MINATEC, France;University of Texas Austin;Integrated Systems Laboratory (LSI), EPFL, Switzerland
Venue:
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Year:
2011

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Abstract

3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage of such small contacts, 3DMI enables manufacturing multiple active layers very close to each other. In this work we propose two different strategies of stacking standard cells in 3-D without breaking the regularity of the conventional design flow: a) Vertical stacking of diffusion areas (Intra-Cell stacking) that supports complete reuse of 2-D physical design tools and b) vertical stacking of cells over others (Cell-on-Cell stacking). A placement tool (CELONCEL-placer) targeting the Cell-on-Cell placement problem is proposed to allow high quality 3-D layout generation. Our experiments demonstrate the effectiveness of CELONCEL technique, fetching us an area gain of 37.5%, 15.51% reduction in wirelength, and 13.49% improvement in overall delay, compared with a 2-D case when benchmarked across an interconnect dominated low-density-parity-check (LDPC) decoder at 45nm technology node.