The physics of VLSI systems
Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Average interconnection length and interconnection distribution based on rent's rule
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Knapsack problems: algorithms and computer implementations
Knapsack problems: algorithms and computer implementations
A wire length estimation technique utilizing neighborhood density equations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Wirelength estimation based on rent exponents of partitioning and placement
Proceedings of the 2001 international workshop on System-level interconnect prediction
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
Toward better wireload models in the presence of obstacles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Toward better wireload models in the presence of obstacles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Efficient Steiner tree construction based on spanning graphs
Proceedings of the 2003 international symposium on Physical design
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
An Accurate Interconnection Length Estimation for Computer Logic
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
A fast congestion estimator for routing with bounded detours
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Dragon2005: large-scale mixed-size placement tool
Proceedings of the 2005 international symposium on Physical design
Low-power fanout optimization using multiple threshold voltage inverters
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FLUTE: fast lookup table based wirelength estimation technique
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Prediction and reduction of routing congestion
Proceedings of the 2006 international symposium on Physical design
Dragon2006: blockage-aware congestion-controlling mixed-size placer
Proceedings of the 2006 international symposium on Physical design
Low-power fanout optimization using MTCMOS and multi-Vt techniques
Proceedings of the 2006 international symposium on Low power electronics and design
System Level Estimation of Interconnect Length in the Presence of IP Blocks
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluation, prediction and reduction of routing congestion
Microelectronics Journal
Congestion prediction in early stages of physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
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With the increasing sophistication of circuits and specifically in the presence of IP blocks, new estimation methods are needed in the design flow of large-scale circuits. Up to now, a number of post-placement congestion estimation techniques in the presence of IP blocks have been presented. In this paper we present a unified approach for predicting wirelength, congestion and delay parameters early in the design flow. We also propose a methodology to integrate these prediction methods into the placement framework to handle the large complexity of the designs.