Ultra large scale integrated microelectronics
Ultra large scale integrated microelectronics
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On wirelength estimations for row-based placement
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Efficient representation of interconnection length distributions using generating polynomials
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Why interconnect prediction doesn't work
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
A priori system-level interconnect prediction: Rent's rule and wire length distribution models
Proceedings of the 2001 international workshop on System-level interconnect prediction
Toward better wireload models in the presence of obstacles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Toward the accurate prediction of placement wire length distributions in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IBM Journal of Research and Development - POWER5 and packaging
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
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Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probability function that assigns a probability to each of these paths to be occupied by a wire. In this paper, we apply a generating polynomial technique to derive complete expressions for site density functions which take effects of layout region aspect ratio and the presence of obstacles into account. The effect of an obstacle is separated into two parts: the terminal redistribution effect and the blockage effect. The layout region aspect ratio and the obstacle area are observed to have a much larger effect on the wirelength distribution than he obstacle's aspect ratio and location. Accordingly, we suggest that these two parameters be included as indices of lookup tables in wireload models. Our results apply to a priori wirelength estimation schemes in chip planning tools to improve parasitic estimation accuracy and timing closure; this is particularly relevant for system-on-chip designs where IP blocks are combined with row-based layout.