RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On wirelength estimations for row-based placement
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Efficient representation of interconnection length distributions using generating polynomials
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Why interconnect prediction doesn't work
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Design technology productivity in the DSM era (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Toward better wireload models in the presence of obstacles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dragon2006: blockage-aware congestion-controlling mixed-size placer
Proceedings of the 2006 international symposium on Physical design
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Fast, accurate a priori routing delay estimation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
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Efficient and accurate interconnect estimation is crucial to design convergence. With System-on-Chip design, IP blocks form routing obstacles that cannot be accounted for by existing a priori wirelength estimations. In this paper, we identify two distinct effects of obstacles on interconnection length: (i) changes due to the redistribution of interconnect terminals and (ii) detours that have to be made around the obstacles. Theoretical expressions of both effects for point-to-point nets with a single obstacle are derived and compared to experimental observations. We also experimentally assess these effects for multi-terminal interconnections and in the presence of multiple obstacles. We single out cases where the effects are additive, which suggests the use of lookup tables and equivalent blockage relations. Our results are applicable in chip planning tools, where they enable improved accounting for obstacles in a priori wirelength estimation schemes.