High-level power estimation with interconnect effects
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A Game-Theoretic Approach for Binding in Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Estimating detection probability of interconnect opens using stuck-at tests
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Detection probabilities of interconnect breaks: an analysis
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Detection probabilities of interconnect breaks: an analysis
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Important layout properties of electronic designs include space requirements and interconnection lengths. A reliable interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths [2]. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process. [2] W. E. Donath. Placement and average interconnection lengths of computer logic. IEEE Transactions on Circuits & Systems, CAS-26: pages 272-277, 1979.