On the Characterization of Multi-Point Nets in Electronic Designs
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Estimations of layout parameters of hierarchical systems
SSST '95 Proceedings of the 27th Southeastern Symposium on System Theory (SSST'95)
An Accurate Interconnection Length Estimation for Computer Logic
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Petri net modeling of gate and interconnect delays for power estimation
Proceedings of the 39th annual Design Automation Conference
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 2002 international symposium on Low power electronics and design
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Petri net modeling of gate and interconnect delays for power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
High-level area and power-up current estimation considering rich cell library
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
IBM Journal of Research and Development - POWER5 and packaging
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We extend earlier work on high-level average power estimation to include the power due to interconnect loading. The resulting technique is a combination of a RTL-level gate count prediction method and average interconnect estimation based on Rent's rule. The method can be adapted to be used with different place and route engines and standard cell libraries. For a number of benchmark circuits, the method is verified by extracting wire lengths from a layout of each circuit and then comparing the predicted (at RTL) power against that measured using SPICE. An average error of 14.4% is obtained for the average interconnect length, and an average error of 25.8% is obtained for average power estimation including interconnect effects.