A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
High-level power estimation with interconnect effects
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Power-simulation of cell based ASICs: accuracy-and performance trade-offs
Proceedings of the conference on Design, automation and test in Europe
Power estimation for large sequential circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Real Delay Switching Activity Simulator based on Petri net Modeling
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Coloured Petri Nets: Basic Concepts, Analysis Methods and Practical Use. Volume 1
Coloured Petri Nets: Basic Concepts, Analysis Methods and Practical Use. Volume 1
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A Hierarchical Colored Hardware Petri net (HCHPN) based model was proposed in [8] for estimating switching activity in combinational circuits. In this paper, we model sequential circuits as HCHPNs incorporating real delays for both gates and interconnects. Thus, the given sequential circuit is first modeled as a HCHPN and simulated for switching activity estimation in the petri net domain which leads to better accuracy and faster simulation. Experimental results for ISCAS'89 benchmark circuits show that the proposed HCHPN model yields accuracy on an average within 4.4% of that of PowerMill. The per-pattern simulation time for HCHPNs is about 2.4 times lesser than that of PowerMill.