Analysis of glitch power dissipation in CMOS ICs
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
New approach in gate-level glitch modelling
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Analysis and reduction of glitches in synchronous networks
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Parallel mixed-level power simulation based on spatio-temporal circuit partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling
Proceedings of the 2002 international symposium on Low power electronics and design
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A Real Delay Switching Activity Simulator based on Petri net Modeling
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Petri net modeling of gate and interconnect delays for power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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