Self-adjusting binary search trees
Journal of the ACM (JACM)
Components quality/reliability handbook
Components quality/reliability handbook
Re-encoding sequential circuits to reduce power dissipation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Power estimation methods for sequential logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Feedback, correlation, and delay concerns in the power estimation of VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Extreme delay sensitivity and the worst-case switching activity in VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power estimation in sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Switching activity analysis using Boolean approximation method
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Statistical estimation of sequential circuit activity
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power estimation techniques for integrated circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Inaccuracies in power estimation during logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Stratified random sampling for power estimation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
State assignment for FSM low power design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
New approach in gate-level glitch modelling
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Effects of correlations on accuracy of power analysis—an experimental study
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Tools and methodologies for low power design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Statistical estimation of average power dissipation in sequential circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Gate-level power and current simulation of CMOS integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power-simulation of cell based ASICs: accuracy-and performance trade-offs
Proceedings of the conference on Design, automation and test in Europe
Trace-driven steady-state probability estimation in FSMs with application to power estimation
Proceedings of the conference on Design, automation and test in Europe
Power estimation for large sequential circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory power models for multilevel power estimation and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors
Proceedings of the conference on Design, automation and test in Europe
Improved Power Estimation For Behavioral and Gate Level Designs
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Markovian analysis of large finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An interconnect energy model considering coupling effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Distributed power-management techniques for wireless network video systems
Proceedings of the conference on Design, automation and test in Europe
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This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods.