Stratified random sampling for power estimation

Authors:
Chih-Shun Ding;Cheng-Ta Hsieh;Qing Wu;Massoud Pedram
Affiliations:
Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA;Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA;Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA;Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
Venue:
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Year:
1997

Citing 3
Cited 10

Estimation of average switching activity in combinational and sequential circuits

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Switching activity analysis considering spatiotemporal correlations

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Efficient estimation of dynamic power consumption under a real delay model

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

High-level power modeling, estimation, and optimization

DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast power estimation for deterministic input streams

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Stream synthesis for efficient power simulation based on spectral transforms

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Improving sampling efficiency for system level power estimation

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
On mixture density and maximum likelihood power estimation via expectation-maximization

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A Markov chain sequence generator for power macromodeling

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multimode power modeling and maximum-likelihood estimation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Monitoring Large Systems Via Statistical Sampling

International Journal of High Performance Computing Applications
Efficient algorithms for multilevel power estimation of VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propose a statistical power evaluation framework at the RT-level. We first discuss the power macro-modeling formulation, and then propose a simple random sampling technique to alleviate the the overhead of macro-modeling during RTL simulation. Next, we describe a regression estimator to reduce the error of the macro-modeling approach. Experimental results indicate that the execution time of the simple random sampling combined with power macro-modeling is 50 X lower than that of conventional macro-modeling while the percentage error of regression estimation combined with power macro-modeling is 16 X lower than that of conventional macro-modeling. Hence, we provide the designer with options to either improve the accuracy or the execution time when using power macro-modeling in the context of RTL simulation.