Improving sampling efficiency for system level power estimation

Authors:
Chih-Shun Ding;Cheng-Ta Hsieh;Massoud Pedram
Affiliations:
Rockwell Semiconductor Systems, Rockwell International Corporation, Newport Beach, CA;Department of Electrical Engineering - Systems, University of Southern California Los Angeles, CA;Department of Electrical Engineering - Systems, University of Southern California Los Angeles, CA
Venue:
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Year:
1998

Citing 2
Cited 0

Stratified random sampling for power estimation

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

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Abstract

In this paper, we propose an efficient statistical sampling technique which is suitable for estimating the total power consumption of a large VLSI system. The basic idea is to generate simulation units for each module in the system independently and then form samples of the system power by randomly selecting simulation units for each module. Hence, sampling is performed both temporally (across different clock cycles) and spatially (across different modules). A module clustering step ensures that the module types are compatible with this sampling strategy. Experimental results show a 4x reduction in the simulation time compared to existing Monte-Carlo simulation techniques.